Curriculum Calendar

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All class times are listed in Eastern Time
All classes will consist of a 45 minute lecture and an interactive chat session
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Archived Tracks
Intelligent Embedded Systems for the New Era of Industrial Apps  
Monday, November 26 - Friday, November 30
SPONSORED BY
Date Class   Status   Lecturer
Nov 26
12PM
Introduction: Understanding the Connected Factory of the Future & Next-Gen Industrial Apps
In this class, you'll learn how the flexible, digital factory of the future will dominate the industrial arena, what its components are, and how embedded apps are evolving to serve this new environment.
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Brian Bailey  
Brian Bailey is an independent engineering consultant working in the fields of Electronic System Level (ESL) methodologies and ...  
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Brian Bailey
Brian Bailey

Brian Bailey is an independent engineering consultant working in the fields of Electronic System Level (ESL) methodologies and functional verification of embedded systems. He was previously chief technologist for verification at Mentor Graphics, where he pioneered work on hardware/software co-design and co-verification. He is the editor for the EETimes Designlines and a contributing editor to EDN. Embedded systems are the point where hardware and software come together, and this is where Brian Bailey has spent most of his working career, first as a tool developer, then as an architect, and later as a technology writer. He has concentrated on the impact that hardware and software can have on each other and the ways in which this is changing over time into the heterogeneous, concurrent, connected applications of today. He has published seven books, given talks around the world, chairs international standards committees, and sits on the technical advisory board for several EDA companies. He graduated from Brunel University in England with a first class honors degree in electrical and electronic engineering.


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Nov 27
12PM
Part II: Four Pillars of Intelligent Industrial Apps: Security, Manageability, Connectivity & Performance
This lecture will give engineers' perspective about crossing the bridge from the traditional embedded perspective to intelligent applications, which are more adaptive and responsive to user needs throughout their lifecycle. We'll define the four pillars of these apps in the context of both engineering requirements and customer benefits.
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Nov 28
12PM
Part III: Rethinking Embedding Processing: The Bridge to Ivy Bridge
Traditional embedded solutions have drawn from a disparate range of CPU solutions. Emerging, next-gen intelligent apps by definition require a minimum of 32-bits for optimum functionality. We'll dive into the architecture and features of one such family, the third-generation Intel Core vPro Processors, which include multiple x86-64 cores and embedded security.
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Nov 29
12PM
Part IV: Apps Development Utilizing the Partner Ecosystem of Intelligent Solution
To help engineers ensure that end-user specs and constraints are factored into the design equation -- with the output being a reliable, cost-effective end product -- we'll examine the rich ecosystem of boards, operating systems, security solutions, and tools available for building your intelligent app.
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Nov 30
12PM
Part V: Case Study: Highlighting a Successful Design Example
Putting it all together is where the rubber meets the road in any embedded effort. We'll delve into a successful design project, which showcases how engineers at an energy company put to practical use the intelligent concepts discussed in this course to create a noteworthy application.
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All Programmable FPGAs and SoCs for Fast, Cost-Effective Designs  
Monday, December 10 - Friday, December 14
SPONSORED BY
Date Class   Status   Lecturer
Dec 10
12PM
Part I. Introduction: The Basics & Benefits of All Programmable Devices
In this session you will learn about the fundamental lookup table (LUT)-based programmable fabric, along with more sophisticated architectures featuring memory blocks, DSP blocks, and hard and soft processor cores. The various technologies used to create different types of programmable devices -- including antifuse, Flash, and SRAM-based devices -- will be discussed, along with their advantages and disadvantages.
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Max Maxfield  
Max Maxfield is editor in chief of All Programmable Planet, a site about all things programmable. He received his BSc in Control ...  
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Max Maxfield
Max Maxfield

Max Maxfield is editor in chief of All Programmable Planet, a site about all things programmable. He received his BSc in Control Engineering in 1980 from Sheffield Hallam University in Sheffield, UK. He began his career as a designer of central processing units (CPUs) for mainframe computers. Over the years, Max has designed everything from silicon chips to circuit boards, and from brainwave amplifiers to steampunk "Display-O-Meters." He has also been at the forefront of Electronic Design Automation (EDA) for more than 20 years.

Max has authored and co-authored a number of books, including Designus Maximus Unleashed! (banned in Alabama), Bebop to the Boolean Boogie: An Unconventional Guide to Electronics, EDA: Where Electronics Begins, FPGAs: Instant Access, and How Computers Do Math.


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Dec 11
12PM
Part II. Understanding the Role of Hardware Description Languages (HDLs)
In this session, you will be introduced to a number of hardware description languages (HDLs), including Verilog, VHDL, SystemVerilog, and SystemC. The differences between HDLs and traditional programming languages like C/C++ will be discussed, along with the difference in hardware-centric versus software-centric design flows.
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Dec 12
12PM
Part III. Design Tools and Methodologies
In this session, you will learn about the various tools and techniques that may be used to capture All Programmable FPGA and SoC designs. These range from textual descriptions to graphical entry mechanisms, and from hand-coding to high-level synthesis (HLS).
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Dec 13
12PM
Part IV. Programming, Debugging, Verifying & Protecting Designs
In this session, you will discover the various ways in which a design may be loaded into an All Programmable FPGA and/or SoC. Also discussed will be various debugging and verification techniques, along with ways to protect your designs from copying, cloning, overproduction, and other forms of attack.
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Dec 14
12PM
Part V. Advanced Concepts & Future Trends
This final session will cover a wide range of topics, including high-speed serial interconnect, optical interconnect, programmable analog fabric, 3D All Programmable chip technologies, and tools and techniques for creating radiation tolerant All Programmable designs.
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Wireless for Miniaturized Consumer Electronics & Mobile Products  
Monday, January 14 - Friday, January 18
SPONSORED BY
Date Class   Status   Lecturer
Jan 14
12PM
Introduction: Understanding the Different Flavors of IEEE 802.11
Attendees will come away from this EE Times University track with an understanding of the alphabet soup of 802.11 specifications, as well as a brief history of the technology. They'll also learn about mainstream chipsets and reference designs and what's due to emerge in the near future.
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Fanny Mlinarsky  
Fanny Mlinarsky has 28 years of experience developing data communication and test products. As President of octoScope ...  
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Fanny Mlinarsky
Fanny Mlinarsky

Fanny Mlinarsky has 28 years of experience developing data communication and test products. As President of octoScope (2006–present) she is responsible for the development of wireless test solutions. From 2001 to 2006 she was founder and CTO of Azimuth Systems, the leading wireless test equipment vendor of WiFi, WiMax, and LTE test systems. As VP of Engineering at Scope Communications (now Agilent), Fanny and her team developed network test equipment (1993–2001). She has published more than 50 articles and whitepapers on wireless technologies and standards and is a frequent presenter at industry conferences. She actively participates in industry standards development at IEEE and 3GPP.


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Jan 15
12PM
Part II: MIMO or SISO? Wireless Board Design Considerations & Trade-Offs
This class will discuss the basics of MIMO radio technology, present real-life measurements of MIMO versus SISO performance, and discuss the cost/performance/power consumption trade-offs of different design approaches.
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Jan 16
12PM
Part III: Bluetooth
Today's lecture will cover the evolution of Bluetooth, including Bluetooth 3.0 and 4.0; give an overview the Bluetooth protocol and standards; and examine the capabilities of available devices.
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Jan 17
12PM
Part IV: Standards-Based vs. Proprietary Wireless Implementations
In this lecture, we'll learn about proprietary wireless solutions and tradeoffs of proprietary versus standards-based radio design for a variety of applications.
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Jan 18
12PM
Part V: Challenges of RF Test, Integration & Compliance in the Final Product
Today's session will cover industry-accepted test methods and metrics at different stages of product lifecycle, including R&D, certification, QA, production, and field testing.
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